An area-delay efficient Radix-8 12x12 Booth multiplier in CMOS for ML accelerator

EDP Sciences, Department of Electronics Communication Engineering, Sreenidhi Institute of science and technology, Hyderabad

^* Corresponding author: abhishek.c@sreenidhi.edu.in

Abstract

The multiplier is a significant module of graphics processing units (GPUs) and digital signal processing (DSP). These applications need low power consumption. This paper proposes a low-power radix-8 12-by-12 Booth multiplier. The proposed radix-8 Booth multiplier is implemented using an optimized Binary to 2-’s complement (B2C), convertor, and optimized multiplexer at each stage of the Booth multiplier architecture. The proposed architecture uses 23% less power and 12% less delay compared to existing architecture. To validate the results, all designs are synthesized using Cadence CMOS technology 45nm.