Design of clock and data recovery system ’s behavioral model for high speed transceivers of serial interfaces

. This paper provides a parameterizable behavioral model of a clock and data recovery system (CDR) based on phase-locked loop (PLL) for the receiver part of a high-speed serial interfaces. The model was used to calculate parameters and characteristics of the system as well as estimate their calculation error depending on the sub-circuit characteristics taken into account. A model structure was selected based on the obtained jitter estimation error. The model complies with all the accuracy and speed requirements to calculations of the characteristics of a PLL-CDR system for a receiver block with data transmission bit rates above 3.125 Gbit/s.


Introduction
The system of Clock and Data Recovery (CDR) is an integral part of high-speed transceivers of serial interfaces. A CDR system based on a PLL (phase-locked loop) circuit with a "bang-bang" phase detector [1] is a common type of CDR system architecture [2].
High-level behavioral models have gained widespread use at the stage of PLL-CDR system characterization. A behavioral model uses parameters of certain sub-circuits of the transistor model, which enables highly accurate calculations at the stage of behavioral modelling of the system. Behavioral models used at schematic design step have the following advantages: -unlike analytical methods [3][4][5], modelling allows describing not only the steadystate operating mode of the system, but also the initial transition process.
-simulation of a behavioral model is several times faster than simulation of the electric circuits, their components being represented by physical models of BSIMv4 type (the reference model).
However, behavioral models require, firstly, estimation of the calculation error because they do not take into account all the characteristics of electric circuits of the reference model; and secondly, determination of a set of parameters to take into account to achieve an acceptable calculation error. The value of error depends on the relation between deterministic jitter J D of the receiver clock signal and the value of bit interval UI. The calculation for the transceiver reference model shows that the value of J D for the speed of 3.125 Gbit/s is ~8 ps at UI = 320 ps. As far as J D << UI, the relative error of determinate jitter calculation (relative to the reference model) of δJ D < 50% is acceptable for this purpose. The paper estimates the error of parameters calculation performed using the PLL-CDR behavioral model and the influence of sub-circuit parameters and characteristics on the error. To check the results, a behavioral model of PLL-CDR system for a receiver with the bit rate of 3.125 Gbit/s was developed using Verilog-AMS hardware description language followed by a comparison with the reference model.

Main parameters and characteristics of the system
The following parameters and characteristics describe the transition process of frequency F RX (t) and phase φ RX (t) of the receiver clock signal being recovered : 1. Transition time τ CDR to locked state; 2. Maximum allowed initial relative frequency difference: where F BIT is input data bit rate, and N -initial step bit frequency step-down ratio (depends on the receiver architecture); 3. Deterministic jitter: where UI = (2 • <F BIT >) -1 , <F RX > and <F BIT > -average values of the corresponding parameters, and Δφ RX max -the amplitude of oscillations φ RX (t) measured in the locked state. 4. JTF(f Jin ) jitter transfer function -the ratio between output jitter amplitude A Jout and input jitter amplitude A Jin depending on the frequency of change A Jin . 5. KJ(A Jin ) determinate jitter transfer ratio -the ratio between output jitter amplitude A Jout and input determinate jitter amplitude A Jin . Figure 1 shows an overview diagram of PLL-CDR. Each of the sub-circuits and its models are described below. T H fall times of the input flip-flops. Accordingly, two behavioral models represent the block: including these parameters (PD SH ) or excluding them (PD F ).

Sub-circuits of the system and their parameters
The charge pump (ChP) block transforms signals nUp and Dn into the charge and discharge current of the lowpass filter. The main parameters of it are charge current I P , discharge current I N , current mismatch ΔI = (I P -I N )/(I P + I N ) and the dependency of these currents from the output voltage I P (U REG ), I N (U REG ). Therefore, the paper presents three models of ChP: with balanced currents (ChP F ), with account of current mismatch (ChP UC ) and with account of the dependency from the operation point (ChP OP ). PLL-CDR uses lowpass second-order filter.
The voltage-controlled oscillator (VCO) is characterized by voltage-frequency characteristic K VCO . The paper proposes two behavioral models of the voltage-controlled oscillator: linear voltage-frequency characteristic with the sloping calculated for (VCO LN ) operating point and a voltage-frequency characteristic taking into account the operating point (VCO NLN ).
The equivalent feedback circuit delay τ LB determines the total delay in all sub-circuits in the PD -ChP -VCO path. Table 1 lists the general information about the sub-circuit models described above.

Error estimation of the behavioral model
The procedure of error estimation for each of the parameters of the sub-circuits listed in table 1 is as follows : 1. The sub-circuit of the reference model is substituted by its behavioral model. 2. The parameters of this model are calculated and compared to those of the reference model.
3. The procedure is repeated for a more complex sub-circuit model. Table 2 shows the results of PLL-CDR system modelling in the time domain consisting of sub-circuit combinations described above and relative errors with respect to the reference model for each of the parameters. The modelling conditions: K.28.5 sequence of 8B/10B code. As far as the time required for determining parameter δF max (0) is comparable to that of the reference model calculation even when one of the sub-circuits is substituted by a behavioral model, the calculation was performed using only the behavioral model consisting of the models with the least error of parameter J D .
The maximum J D error reduction takes into account the dependency of the output ChP current from the operational point.   Figure 2 shows the influence of value τ LB on value J D . The dependency has non-linear nature and disrupts the relation δJ D < 50% only when the value τ LB is more than 3.4 times different from that for the reference model.   A similar comparison has been performed for characteristic KJ(A Jin ). Figure 4 shows the corresponding dependency. The conditions: input code K.28.5 of 8B/10B code with deterministic jitter. The value of the input jitter varies in the range from 0.1 UI to 0.5 UI.
The error of the model across the whole range does not exceed 36 % (in 0.1 UI point). The calculations show that the developed model consisting of PD SH + ChP OP + VCO NLN meets the requirement of δJ D < 50% and is suitable for PLL-CDR system parameter estimation.

Conclusion
Different options for behavioral models of PLL-CDR sub-circuits were studied. The error of behavioral models of sub-circuits was analysed in comparison with the reference BSIMv4 type model depending on the sub-circuit parameters. A parametrizable behavioral model of PLL-CDR system complying with the error requirement was developed using Verilog-AMS hardware description language. The value of deterministic jitter J D obtained using the behavioral model is 8.1 ps, and that obtained using the reference model is 7.8 ps. Therefore, the relative error of determinate jitter δJ D calculation is less than 4%.
The error of KJ(A JD ), JTF(f Jin ) calculation does not exceed 36%. The developed model allows calculating the transition process of PLL-CDR system ~10 3 times as fast as the reference model and calculating BER using method [6]. The developed model can be used to calculate PLL-CDR characteristics with arbitrary bit rate.