| Issue |
ITM Web Conf.
Volume 74, 2025
International Conference on Contemporary Pervasive Computational Intelligence (ICCPCI-2024)
|
|
|---|---|---|
| Article Number | 02006 | |
| Number of page(s) | 7 | |
| Section | Cybersecurity, Networks, and Computing Technologies | |
| DOI | https://doi.org/10.1051/itmconf/20257402006 | |
| Published online | 20 February 2025 | |
Implementation of RISC-V Processor
Department of ECE, Sri Venkateswara College of Engineering, Tirupati, India
Department of ECE, Sri Venkateswara College of Engineering, Tirupati, India
This work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in AI, signal processing and cryptography. Design of processor will be implemented by using Verilog/VHDL and simulation tools later it will be tested on FPGA hardware. This project in designing to improve the performance mainly used for high-performance application.
© The Authors, published by EDP Sciences, 2025
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.