Design And Analysis Of 5 Stage Pipelined CPU With Hazard Handling

Electronics and Communication Engineering, St. Joseph’s College of Engineering, Chennai, India

Abstract

This paper compares two different RISC instruction set architectures, one with minimal hazard control and the other with enhanced design, using forward, interlock and special register hazard handling techniques to minimize the effects of hazards on the operating speed of both systems. Both systems were modelled and synthesized using the Xilinx Vivado Toolchain. The results showed a 92.4% decrease in the time required to resolve a hazard, as well as a 38% decrease in stall cycles needed in the enhanced processor compared to the basic processor. The final synthesis of both designs placed them on a Xilinx Artix-7 Field Programmable Gate Array (FPGA) and determined the maximum operating frequency of 167 MHz for the enhanced design, using approximately 12,800 look-up tables (LUTs). Based on this information, the authors conclude that the enhancements to the processor will increase performance and user-friendliness for embedded applications requiring high performance.