| Issue |
ITM Web Conf.
Volume 45, 2022
2021 3rd International Conference on Computer Science Communication and Network Security (CSCNS2021)
|
|
|---|---|---|
| Article Number | 01029 | |
| Number of page(s) | 7 | |
| Section | Computer Technology and System Design | |
| DOI | https://doi.org/10.1051/itmconf/20224501029 | |
| Published online | 19 May 2022 | |
Research on heterogeneous acceleration platform based on FPGA
School of Information Science and Engineering, Yunnan University, Kunming 650500, China
* Corresponding author: 519207213@qq.com
In the context of today’s artificial intelligence, the volume of data is exploding. Although scaling distributed clusters horizontally to cope with the increasing demands on computing power for massive data processing is feasible. But the unlimited addition of nodes will lead to bloated cluster size. Most of the transistors in CPUs are used to build cache memory and control units, which are not efficient for computing operations of massive data processing. Currently, academia uses hardware devices such as GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) to accelerate deep learning, image processing, which require massive computational operations. The paper first discussed the advantages and technical requirements of FPGA acceleration based on the characteristics of the Spark cluster. Then the paper proposed the design of the FPGA-CPU heterogeneous acceleration platform, and introduced the base-two-FFT algorithm. Finally, the paper present and compared the computation time of the base-two-FFT algorithm before and after the acceleration. The results show that the heterogeneous cluster has a speedup ratio of about 1.79 times compared to the CPU cluster.
© The Authors, published by EDP Sciences, 2022
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