Integrating AI into Semiconductor Design and Fabrication: Methodologies, Challenges and Future Prospects

Glasgow College, University of Electronic Science and Technology of China, Chengdu, China

3073728C@student.gla.ac.uk

Abstract

Semiconductor chips underpin modern electronics, yet conventional design and fabrication methods face escalating costs and diminishing returns as device geometries shrink. This review surveys the integration of artificial intelligence (AI) across chip development workflows, categorizing methodologies into supervised machine learning (e.g., SVM, decision trees), deep learning (CNN, RNN/LSTM/GRU, GAN), other AI paradigms (reinforcement, active, transfer learning; genetic algorithms; Bayesian optimization), and hybrid frameworks. In chip design, AI accelerates layout optimization, power‐performance trade‐off, and defect classification, while in fabrication it enhances wafer‐level defect detection, process monitoring, and production scheduling. Case studies illustrate GAN–CNN hybrids for noise‐robust fault diagnosis and GA–SVM/DT pipelines for failure prediction. Despite notable successes—such as sub‐nanometer feature prediction and real‐time anomaly detection—key challenges persist: scarcity of high‐quality, labeled datasets due to proprietary restrictions; the “black‐box” nature of deep models impeding interpretability; and a shortage of interdisciplinary expertise bridging AI and semiconductor domains. Future research should prioritize development of explainable models, federated or synthetic data generation strategies, and cross‐domain education to cultivate hybrid talent.