Design and Analysis the Performance of Ternary Logic Gates using Doping-Less FET

¹ Department of Electronics and communication engineering, St.Joseph’s college of Engineering Chennai, Tamilnadu,India This email address is being protected from spambots. You need JavaScript enabled to view it.
² Department of Electronics and communication engineering, St.Joseph’s college of Engineering Chennai, Tamilnadu,India This email address is being protected from spambots. You need JavaScript enabled to view it.
³ Department of Electronics and communication engineering, St.Joseph’s college of Engineering, Chennai, Tamilnadu,India This email address is being protected from spambots. You need JavaScript enabled to view it.

Abstract

This paper presents the analysis of performance and design of ternary logic gates using doping- less field-effect transistors (DLFET) integrated with resistive memory (RM). The goal which we’re trying to achieve is low-power, high-speed operation suitable for multi-valued logic systems. The key ternary gates— Inverter, NAND, and NOR—are designed using DLFET-RM architecture and evaluated. Their performance is compared against conventional and emerging technologies, including Single Gate MOSFET, Double Gate MOSFET, FET, CNFET, and FINFET. Parameters such as power consumption, propagation delay, and power-delay product (PDP) are used as the basis for comparison. Significant reductions are shown for both delay and PDP in the simulation results for the proposed design. Compared to traditional logic gates, the DLFET-RM gates achieve up to 90% improvement in PDP . These improvements are hugely due to the doping-less structure, which avoids random dopant fluctuations, and the efficiency of RM elements. By eliminating the need for passive resistors, the proposed circuits also reduce area and complexity. Overall, DLFET-RM-based ternary logic is shown to be a ideal candidate for future low-power nanoelectronic systems.