High-Speed AXI4-Lite Dynamic MAC Accelerator for RISC-V SoC Designs

¹ Department of ECE, St. Joseph’s Institute of Technology
² Professor (Department of ECE), St. Joseph’s Institute of Technology

^* Corresponding author: This email address is being protected from spambots. You need JavaScript enabled to view it.

Abstract

This design and realization of a high-speed dynamic-precision Multiply–Accumulate (DPMAC) accelerator targets embedded and RISC-V-based System-on-Chip (SoC) platforms. Unlike conventional MAC units that operate with a fixed precision, this design supports runtime configurable 8-, 16-, and 32-bit precision modes. These modes allow accuracy, energy efficiency, and operational behaviour to be tuned according to workload requirements, while the pipeline maintains the same latency for all modes. The dynamic-precision MAC’s data-path integrates Radix-4 Booth multiplier and Brent– Kung adder within a two-stage pipeline, ensuring deterministic and low-latency operation regardless of precision selection. The AXI4-Lite interface enables communication with processor subsystems through memory-mapped registers, providing flexible configuration and control of precision, start/enable logic, and accumulator behaviour. Through FPGA synthesis and testing, the proposed AXI-MAC unit demonstrates competitive timing and resource utilization while offering improved numerical flexibility compared to traditional fixed-precision MAC units. The absence of DSP slice requirements further enhances portability across devices. As such, the architecture provides an efficient, high-performance, and scalable solution suitable for next-generation embedded computing and edge-processing applications.