ITM Web Conf.
Volume 7, 20163rd Annual International Conference on Information Technology and Applications (ITA 2016)
|Number of page(s)||6|
|Section||Session 4: Information System and its Applications|
|Published online||21 November 2016|
A Testable Design Method for Memories by Boundary Scan Technique
School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China
This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC). The feature of the Flash TAP (Test Access Port) complies with the IEEE std.1149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test) circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.
© Owned by the authors, published by EDP Sciences, 2016
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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