FPGA Implementation of Enhanced Montgomery Modular for Fast Multiplication

^1,2 Department of Electronics and Instrumentation Engineering, Shri G.S. Institute of Technology and Science, Indore, India
³ Department of Biomedical Engineering, Shri G.S. Institute of Technology and Science, Indore, India

^* Akanksha Jain: akanksha28.aj@gmail.com

Abstract

This Paper proposed an enhanced Montgomery and efficient implementation of Modular Multiplication. Cryptographyoprocess is usedufor providingphigh informationmsecurity when a data is transferredmfrom transmitter to receiver. Various using methods like RSA, ECC, the Digital Signature Algorithm. The propose Montgomery algorithm usin RSA algorithim of cryptography is implemented in two different input both the inputs are 8 bit input. Coding have been done in Verilog language and the results are simulated on Vivado Software. For physical testing, we have used an FPGA NESYS 4 DDR hardware board that have Artix-7 FPGA chip on it produced by digilent company. The propose method shows good results in term of the number of slice flip flop, LUTs, and number of IOBs and power consumption. The proposed method shows better results as compare to other previous methods in term of different result parameters.