Design and Implementation of Braun Multiplier with Different Adder Architectures

¹ Department of Electronics and Communication, KLE Technological University, Hubballi, India e-mail: 01fe22bec250@kletech.ac.in,suhasshirol@kletech.ac.in
² Department of Electrical and Electronics, KLE Technological University, Hubballi, India e-mail: 01fe22bee055@kletech.ac.in,01fe22bee069@kletech.ac.in

^* Corresponding author: suhasshirol@kletech.ac.in

Abstract

This paper presents a high-performance, scalable Braun multiplier architecture implemented on FPGA, featuring advanced and hybrid adder topologies for enhanced power, area, and timing efficiency. The proposed system integrates Ripple Carry Adders (RCA), Brent-Kung Adders (BKA), Kogge-Stone Adders (KSA), and hybrid variants using structural Verilog, targeting both 4-bit and 32-bit designs. To address the limitations in conventional designs, this work introduces formal mathematical formulations for prefix logic, provides an algorithmic breakdown of carry propagation, and conducts a detailed power-delay-area (PDA) analysis. Implementations were carried out on a Xilinx Spartan-6 FPGA with post-place-and-route timing evaluation. Comparative analysis shows BKA yields the lowest LUT usage, while KSA achieves the minimum delay, making each suitable for low-power and high-speed applications respectively. Real-time signal monitoring using ChipScope ICON/VIO facilitates hardware-level debugging. The design offers a practical, energy-efficient, and modular solution for arithmetic-intensive applications in VLSI, embedded systems, and digital signal processing.