Open Access
| Issue |
ITM Web Conf.
Volume 79, 2025
International Conference on Knowledge Engineering and Information Systems (KEIS-2025)
|
|
|---|---|---|
| Article Number | 01009 | |
| Number of page(s) | 8 | |
| DOI | https://doi.org/10.1051/itmconf/20257901009 | |
| Published online | 08 October 2025 | |
- B. Neeraja, R.S.P. Goud, Design of an Area Efficient Braun Multiplier Using High Speed Parallel Prefix Adder in Cadence, In 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT) (IEEE, 2019), pp. 1–5, https://doi.org/10.1109/ICECCT.2019.8869307 [Google Scholar]
- R. Anitha, V. Bagyaveereswaran, FPGA Implementation of Braun’s Multiplier Using Spartan- 3E, Virtex-4, Virtex-5 and Virtex-6, In International Conference on Web and Semantic Technology (Springer, 2011), Vol. 197 of Communications in Computer and Information Science, pp. 486–494, https://doi.org/10.1007/978-3-642-22543-7_49 [Google Scholar]
- K. Kalaikaviya, M. Suba, S. Sudha, Design of Low Area Braun Multiplier with Brent–Kung Adder, In ICCSP’13: International Conference on Communications, Signal Processing and their Applications (IEEE, 2013), pp. 447–450, available online: https://www.academia.edu/download/34896488/42_T1.pdf [Google Scholar]
- S. Karunakaran, B. Poonguzharselvi, Vlsi architecture of an 8-bit multiplier using vedic mathematics in 180nm technology, International Journal of Advances in Engineering & Technology 10, 401 (2017), available online: https://www.ijaet.org/media/14I39-IJAET1003317-v10-i3-pp401-410.pdf. [Google Scholar]
- B. Bandre, Design and analysis of low power energy efficient braun multiplier, International Journal of New Practices in Management and Engineering 2, 08 (2013). 10.17762/ijnpme.v2i01.12 [CrossRef] [Google Scholar]
- S.B. Shirol, S. Ramakrishna, R.B. Shettar, in Computing and Network Sustainability: Proceedings of IRSCNS 2018 (Springer, 2019), pp. 239–249, https://doi.org/10.1007/978-981-13-7150-9_25 [Google Scholar]
- D.K. D.K., S. R., K. B.S., VLSI Implementation of Braun Multiplier using Full Adder, in 2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC) (IEEE, 2017), pp. 499–504, https://doi.org/10.1109/CTCEEC.2017.8455157 [Google Scholar]
- S.B. Shirol, S. Ramakrishna, R.B. Shettar, Designing power-efficient bist architecture: Leveraging reversible logic for scalable digital systems, Journal of Electrical Systems 20, 2747 (2024), licensed under CC BY-ND 4.0. 10.52783/jes.2053 [Google Scholar]
- Y. Singh, Semicustom frontend vlsi design and analysis of a 32-bit brent-kung adder in cadence suite, arXiv preprint arXiv:2503.18070 (2025). 10.48550/arXiv.2503.18070 [Google Scholar]
- A. Sharma, A. Mittal, A. Singh, R. Kapoor, Design and implementation of braun multiplier using verilog, In 2024 Asia Pacific Conference on Innovation in Technology (APCIT) (IEEE, 2024), pp. 1–6, https://doi.org/10.1109/APCIT62007.2024.10673483 [Google Scholar]
- M. Sakthimohan, E. Rani, P. Monisha, T. Bhuvaneswari, R. Anand, S.T. Nandhini, An Optimized 4x4 Braun Multiplier for Parallel Processing Architectures with a 3-bit Kogge–Stone Adder, In 2023 International Conference on In-telligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM) (IEEE, 2023), pp. 319–324, https://doi.org/10.1109/iTechSECOM59882.2023.10435221 [Google Scholar]
- K. Yogeshwaran, R. Gowri, S. Sandhya, T. Tejeswar Reddy, T. Vijayalakshmi, Design and Simulation of 16x16 Vedic Multiplier using Kogge–Stone Adder, In 2023 7th International Conference on Computing Methodologies and Communication (ICCMC) (IEEE, 2023), pp. 452–457, https://doi.org/10.1109/ICCMC56507.2023.10083594 [Google Scholar]
- P. Kousalya, M. Lavanya, T. Archana, Carry Tree Adders on FPGA’s Design and its Implementation, In 2024 First International Conference for Women in Computing (InCoWoCo) (IEEE, 2024), pp. 1–5, https://doi.org/10.1109/INCOWOCO64194.2024.10863428 [Google Scholar]
- V. Thamizharasan, N. Kasthuri, Fpga implementation of proficient vedic multiplier architecture using hybrid carry select adder, International Journal of Electronics 111, 1253 (2024). 10.1080/00207217.2023.2245194 [Google Scholar]
- R. Madhuri, P. Bachanna, B. Pavan, M.Z. Begum, Design and Performance analysis of Asynchronous Network on Chip for Streaming data Transmission on FPGA, In 2024 International BIT Conference (BITCON) (IEEE, 2024), pp. 1–6, https://doi.org/10.1109/BITCON63716.2024.10985385 [Google Scholar]
- D. Mittal, Analysis of parallel prefix adders with low power and higher speed, In 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC) (IEEE, 2022), pp. 288–288, https://doi.org/10.1109/ICESC54411.2022.9885726 [Google Scholar]
- I. Omesh, B. Supriya, Y. Yamini, A. Likitha, D. Aditya, Design and implementation of low power and highspeed braun multiplier using hybrid full adder, i-Manager’s Journal on Circuits & Systems 9, 23 (2021). 10.26634/jcir.9.2.16831 [Google Scholar]
- S.V. Padmajarani, M. Muralidhar, Comparison of parallel prefix adders performance in an fpga, International Journal of Engineering Research and Development 3, 62 (2012), https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=9690309826e9b882a430f27c0f737c853832f6e7. [Google Scholar]
- U. Penchalaiah, V.G. Siva Kumar, Design of HighSpeed and Energy-Efficient Parallel Prefix KoggeStone Adder, In 2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCAN) (IEEE, 2018), pp. 1–7, https://doi.org/10.1109/icscan.2018.8541143 [Google Scholar]
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.

