Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits

¹ Associate Professor, Department of ECE, Sri Krishna College of Technology, Coimbatore, Tamilnadu, India
² Associate Professor, Department of ECE, Vel Tech Rangarajan Dr.Sagunthala R&D Institute of Technology, Chennai  
³ Assistant Professor, Department of ECE, Dr.N.G.P Institute of Technology, Coimbatore, Tamilnadu, India
⁴ Assistant Professor, Department of ECE, Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
⁵ Assistant Professor, Department of ECE, Vel Tech Rangarajan Dr.Sagunthala R&D Institute of Technology, Chennai  

Abstract

High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).