EDP Sciences logo
Web of Conferences logo
Search
Menu
All issues Volume 56 (2023) ITM Web Conf., 56 (2023) 01005 References
Open Access
Issue
ITM Web Conf.
Volume 56, 2023
First International Conference on Data Science and Advanced Computing (ICDSAC 2023)
Article Number 01005
Number of page(s) 18
Section Computational Intelligence and Computing
DOI https://doi.org/10.1051/itmconf/20235601005
Published online 09 August 2023
  1. Tang, A., & Jha, N. K. (2016). GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization using Incremental Statistical Analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 1126–1139. [CrossRef] [Google Scholar]
  2. Aras, N., & Yurdakul, A. (2016). A new multi-objective mathematical model for the high-level synthesis of integrated circuits. Applied Mathematical Modelling, 40(3), 2274–2290. [CrossRef] [MathSciNet] [Google Scholar]
  3. Ghandali, S., Alizadeh, B., Fujita, M., & Navabi, Z. (2015). Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Transactions on Computers, 64(6), 1–14. [MathSciNet] [Google Scholar]
  4. Shi, C., & Luo, G. (2018). A Compact VLSI System for Bio-Inspired Visual Motion Estimation. 28(4), 1–16. [Google Scholar]
  5. Cilardo, A., Gallo, L., & Mazzocca, N. (2013). Design space exploration for high- level synthesis of multi-threaded applications. Journal of Systems Architecture, 59(10), 1171–1183. [CrossRef] [Google Scholar]
  6. Qamar, A., Muslim, F. B., Iqbal, J., & Lavagno, L. (2017). LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow. Microprocessors and Microsystems, 50, 26–38. [CrossRef] [Google Scholar]
  7. Prost-Boucle, A., Muller, O., & Rousseau, F. (2014). Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints. Journal of Systems Architecture, 60(1), 79–93. [CrossRef] [Google Scholar]
  8. Pradeep, K. P. S., & Kumar, S. S. (2019). Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing. Cluster Computing, 22, 13387–13395. [CrossRef] [Google Scholar]
  9. Imène, M., Mhadhbi, B. A., & Slim, B. C. (2012). High Level Synthesis Design Methodologies for Rapid Prototyping Digital Control Systems. IFAC Proceedings Volumes, 45(7), 238–243. [Google Scholar]
  10. Campbell, K., Zuo, W., & Chen, D. (2017). New advances of high-level synthesis for efficient and reliable hardware design. Integration, 58, 189–214. [CrossRef] [Google Scholar]
  11. Wilson, D., Shastri, A., & Stitt, G. (2017). A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. International Journal of Reconfigurable Computing, 2017, 1–17. [CrossRef] [Google Scholar]
  12. Bravo, I., Vázquez, C., Gardel, A., Lazaro, J. L., & Palomar, E. (2015). High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem. Mathematical Problems in Engineering, 2015, 1–11. [CrossRef] [Google Scholar]
  13. Chen, Y., Wang, Y., Xie, Y., & Takach, A. (2012). Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing. Journal of Electrical and Computer Engineering, 2012, 1–14. [Google Scholar]
  14. Liang, Y., Rupnow, K., Li, Y., Min, D., Do, M. N., & Chen, D. (2011). High-Level Synthesis: Productivity, Performance, and Software Constraints. Journal of Electrical and Computer Engineering, 2012, 1–14. [CrossRef] [Google Scholar]
  15. Dossis, M. F. (2015). High-level Synthesis Integrated Verification. Engineering, Technology & Applied Science Research, 5(5), 864–870. [CrossRef] [Google Scholar]
  16. Sengupta, A., & Bhadauria, S. (2014). Exploration of Multi-objective Tradeoff during High Level Synthesis using Bacterial Chemotaxis and Dispersal. Procedia Computer Science, 35, 63–72. [CrossRef] [Google Scholar]
  17. Zhao, M., Orailoglu, A., & Xue, C. J. (2015). Joint Profit and Process Variation Aware High Level Synthesis with Speed Binning. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(9), 1640–1650. [CrossRef] [Google Scholar]
  18. Kachave, D., & Sengupta, A. (2016). Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectronics Reliability, 60, 141–152. [CrossRef] [Google Scholar]
  19. Lattuad, M., & Ferrandi, F. (2017). Exploiting vectorization in high level synthesis of nested irregular loops. Journal of Systems Architecture, 75, 1–14. [CrossRef] [Google Scholar]
  20. Hao, C., Ni, J., Wang, N., & Yoshimura, T. (2017). Interconnection Allocation between Functional Units and Registers in High-Level Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(3), 1140–1153. [CrossRef] [Google Scholar]
  21. Kawamura, K., Yanagisawa, M., & Togawa, N. (2013). A Thermal-Aware High- Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96(1), 312–321. [CrossRef] [Google Scholar]

Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.

Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.

Initial download of the metrics may take a while.