| Issue |
ITM Web Conf.
Volume 60, 2024
2023 5th International Conference on Advanced Information Science and System (AISS 2023)
|
|
|---|---|---|
| Article Number | 00010 | |
| Number of page(s) | 6 | |
| DOI | https://doi.org/10.1051/itmconf/20246000010 | |
| Published online | 09 January 2024 | |
Hardware accelerators for processing clusters in binary vectors
1 Institute of Electronics and Informatics Engineering of Aveiro (IEETA), Intelligent Systems Associate Laboratory (LASI), Department of Electronics, Telecommunications and Informatics, University of Aveiro, 3810-193 Aveiro, Portugal
2 Institute of Electronics and Informatics Engineering of Aveiro (IEETA), Intelligent Systems Associate Laboratory (LASI), 3810-193 Aveiro, Portugal
* Corresponding author: iouliia@ua.pt
The paper suggests fast hardware accelerators for discovering clusters of zeros and/or ones in binary vectors. Any cluster is composed of successive bits with the same value (either 1 or 0). Search for such segments is required in many practical problems, for example, coding, data, and image processing. The proposed solutions enable, for a given vector, answering such questions as how many one/zero clusters can be found; what is the largest number of consecutive ones/zeros; what is the number of clusters having k consecutive ones/zeros; is the vector only composed of segments with exactly k consecutive ones/zeros; and some others. The relevant practical applications, for which acceleration is required, are also discussed. The paper suggests two core architectural solutions that are based on combinational and iterative networks of gates. Each network is modeled in software (C++ language) and then specified in a hardware-description language (VHDL), synthesized, and implemented in FPGA. Finally, the results of the circuits’ evaluations and comparisons are presented.
© The Authors, published by EDP Sciences, 2024
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