Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs

¹ Dept. of ECE, Sreenidhi Institute of Science and Technology, Hyderabad - 501 301, Telangana, India
² Dept. of EEE, BITS-Pilani, K K Birla Goa Campus, Sancoale – 403 726, Goa, India

^* Corresponding author: kasi.b@sreenidhi.edu.in

Abstract

This paper presents two novel digital-to-analog converter (DAC) designs that leverage the split capacitor approach. The designs optimize speed, and accuracy, significantly improving linearity and overall performance. Integrating a binary-to-thermometer code (B-TC) decoder at the switching network of the split capacitor techniques further enhances the performance of DACs in terms of linearity, and speed. Also, it reduces the capacitive mismatch associated with capacitive DAC designs. Using Cadence Virtuoso UMC 180nm technology, the designs were implemented with a 90fF capacitance value at 1.8V supply voltage. The performance of these proposed DAC configurations, one with a B-TC decoder and another without is assessed through simulation to benchmark them against state-of-the art designs. According to simulation results, the DAC with an integrated B-TC decoder performs significantly better, which makes it ideal for SAR-ADC design applications that need high speed, low power consumption, and area efficiency.