| Issue |
ITM Web Conf.
Volume 11, 2017
2017 International Conference on Information Science and Technology (IST 2017)
|
|
|---|---|---|
| Article Number | 08006 | |
| Number of page(s) | 9 | |
| Section | Session VIII: Signal Processing | |
| DOI | https://doi.org/10.1051/itmconf/20171108006 | |
| Published online | 23 May 2017 | |
A Coarse-Fine Time-to-Digital Converter
Key Laboratory of Optoelectronic Technology and System, Ministry of Education of the P. R. China, Chongqing 400044, P. R. China
a Corresponding author: silhouette_c@foxmail.com
A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized the dual DLL structure to achieve high precision. The proposed TDC can provide high resolution with less chip area. With an input reference clock of 125MHZ, the TDC achieves 8ps resolution, and the dynamic range achieves 1.5μs.
© Owned by the authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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