ITM Web Conf.
Volume 30, 201929th International Crimean Conference “Microwave & Telecommunication Technology” (CriMiCo’2019)
|Number of page(s)||6|
|Section||Microwave Communication, Broadcasting and Navigation Systems (3)|
|Published online||27 November 2019|
Design of clock and data recovery system’s behavioral model for high speed transceivers of serial interfaces
RnD center "ELVEES", JSC, 124498, Moscow, Zelenograd, proezd 4922, dom 4, stroenie 2, Russia
* Corresponding author: email@example.com
This paper provides a parameterizable behavioral model of a clock and data recovery system (CDR) based on phase-locked loop (PLL) for the receiver part of a high-speed serial interfaces. The model was used to calculate parameters and characteristics of the system as well as estimate their calculation error depending on the sub-circuit characteristics taken into account. A model structure was selected based on the obtained jitter estimation error. The model complies with all the accuracy and speed requirements to calculations of the characteristics of a PLL-CDR system for a receiver block with data transmission bit rates above 3.125 Gbit/s.
© The Authors, published by EDP Sciences, 2019
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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