The Design of An LDO Regulator

National Institute of Technology, Kurukshetra, Haryana, India
National Institute of Technology, Kurukshetra, Haryana, India

32219230@nitkkr.ac.in
chhagan.charan@nitkkr.ac.in

Abstract

In today’s modern systems on chip (SOCs), a crucial power management circuit is the low-dropout (LDO) regulator. Of course, the need for supply voltage regulation, goes back many years in the past since the circuits have been designed. Today, LDO based voltage regulators are frequently used in a number of mixed-signal systems to produce local supply voltages that feed different building blocks. LDOs try to isolate the noise of the circuit and noise from the global supply and try to reduce their effect on device performance. For the state of desired achievement, each LDO’s architecture is circuited to the specific cell it feeds. An LDO designed to feed a flash analog-to-digital converter, for instance, differs greatly from one designed to input a VCO. In this paper, we direct an LDO for a VCO of 5-GHz LC and point the particulars of 1.2 V as input voltage, produces 1V as output voltage, 5 mA of maximum output current, power supply rejection greater than 40 dB up to 10 MHz and noise voltage present at output that is less than 25nV/√Hz at 1 MHz.